In a modern computer system, a memory management task is jointly implemented by an operating system, a memory management unit (MMU), and a translation lookaside buffer (TLB).
In an existing memory management flow, the operating system is responsible for a vast majority of memory management tasks, and tasks of virtual-physical address mapping and page lookup, which are operated most frequently, are implemented by hardware such as the TLB and the MMU. Such a memory management manner has two inherent bottlenecks: (1) The TLB and the MMU are located in a key path of accessing a cache by a processor, and the processor needs to first access the TLB whenever accessing the cache. Once TLB misses increase, the MMU looks up a page frequently, which is likely to cause a system bottleneck. (2) Page fault processing and binding: Once the MMU fails to look up a page, a page fault is triggered, and the processor spends much time in processing the page fault. An average time for a Linux system to look up a page is 35.8 processing periods, and an average time for the Linux system to process a page fault is 2687 processing periods. If the two bottlenecks can be avoided or a quantity of occurrences of the two bottlenecks can be reduced, memory management efficiency of an entire computer system will be enhanced greatly.
In the prior art, an effective memory management technology is proposed: a virtual indexed virtual tagged cache technology. A main conception of a virtual indexed virtual tagged cache is to remove the hardware such as the TLB and the MMU from the key path of accessing the cache, where a program directly uses a virtual address to index the cache, and the TLB performs virtual-physical address translation only after a cache miss, whereupon a physical address is used to access the cache. The method can shorten the key path of accessing the cache by the processor. In addition, because the TLB is not in the key path of accessing the cache, an extremely large scale of the TLB can be accomplished, and a hit rate of the TLB increases, thereby effectively reducing a quantity of TLB misses. Therefore, the virtual indexed virtual tagged cache can effectively alleviate the first inherent bottleneck mentioned above.
However, a manner of processing a page fault is still bound to the processor. No matter whether the page lookup is performed by the MMU hardware or the operating system, the page fault occurs once the page lookup fails. The processor wastes plenty of time in processing the page fault, which leads to low memory management efficiency.